For semiconductor integrated circuit, especially custom LSI, a variety of logic's are required depending on customers, and to shorten the period from receipt of order to delivery of product (shortened TAT(turn-around-time)). However, in conventional stepper exposure, since it is necessary to prepare a mask, it takes a long time for the fabrication process and therefore TAT is difficult to shorten. Also, due to the preparation of mask needed, there is a problem that the cost increases. So, electron beam direct drawing techniques that require no mask are attracting attention. However, in electron beam direct drawing, instead of requiring no mask, drawing data have to be in advance prepared by using CAD etc. Also, to convert the data into a format recognizable by an electron direct drawing system, data conversion is needed. For the data conversion, general-purpose workstations are normally used. Although the conversion time depends on the performance of machine and the amount of data, there occurs a time loss due to this operation. If the preparation of drawing data and the data conversion are conducted after the receipt of an order, TAT becomes difficult to shorten. Therefore, it is desired that, in advance, drawing data are prepared and the data conversion is completed. However, since the drawing data are varied depending on customers, it is impossible, in advance, to prepare the drawing data and to complete the data conversion. So, there has been developed a method where multiple data to each part such as Tr cell, peripheral circuit etc., which are originally a suite of drawing data, are prepared and these data are properly combined and then used to draw an LSI needed. Thereby, the preparation of drawing data and the data conversion can be in advance completed, therefore allowing TAT to be shortened.
FIG. 1 shows an example of such a method. First, there is provided drawing data 1 for a Tr cell, as shown in FIG. 1A. Corresponding to this, there are in advance prepared drawing data 2, 3 and 4 for a peripheral circuits shown in FIGS. 1B 1C and 1D, and their data conversion is completed. By selecting properly the drawing data 2, 3 or 4 for a peripheral circuit, multiple products can be drawn in a short TAT. Thus, when a custom LSI is drawn using electron beam direct drawing, there exist multiple drawing data in the chip.
Next, the operation of drawing such a LSI is explained. First, the drawing of multiple drawing data in the chip by conventional step and repeat (hereinafter referred to as `S & R`) method is explained in FIG. 2. Since, in electron beam direct drawing, the distance that beam can be stably electrically deflected is limited, the chip (drawing data) is divided into fields 72 a size that a beam can be stably deflected, and these fields 72 are combined together to achieve the drawing. In the process of drawing, field center position 73 is moved in directions 74 and 75 to locate at just under the beam (at a position with zero amount of beam deflection) by using the stage, and the stage is stopped at the position. Then, at that position, electron beam 76 is electrically deflected to draw a pattern within the field. This operation is repeated to draw the pattern within each field.
Next, the method of dividing into fields for drawing data is explained. FIG. 3 is the block diagram showing a conventional electron beam direct drawing system. An electron beam direct drawing system 80 is composed of a memory 83, a main body 84 and a drawing control section 85. First, drawing data 81 prepared by using CAD etc. is converted into a format recognizable by the electron beam direct drawing system 80. Then, the drawing data 82 is converted and is transferred and stored in the memory 83 of the electron beam direct drawing system 80. Then, the drawing control section 85 reads the drawing data 82 stored in the memory 83 and divides the drawing data 82 into fields. In the process of dividing, the size of drawing data only is considered. Therefore, the drawing is performed while dividing the drawing data into arbitrary fields and conducting the S&R operation.
Even when there are multiple drawing data in the chip, the same drawing operation is performed. For example, the field dividing operation in case of two drawing data is shown in FIGS. 4A to 4E. The drawing data 81 is of drawing data 1 (Tr cell) shown in FIG. 4B and drawing data 2 (peripheral circuit) shown in FIG. 4C, where the sizes of the drawing data are different. The respective drawing data are, as shown in FIGS. 4D and 4E, overlapped on the sample to form one chip.
First, drawing data 1, 2 are stored in memories 1, 2 of the memory 83 in FIG. 4A. Then, drawing data 1 is first read from memory 1 and then is, as shown in FIG. 4B, divided into fields A and B to D by the drawing control section 85. Then, drawing data 2 is read from memory 2 and then is, as shown in FIG. 4C, divided into fields e and f to m. Then, drawing data 1, 2 are drawn by S & R drawing operation as described above. The field dividing operation is thus conducted on the basis of each of drawing data. Therefore, as shown in FIG. 4E, the fields A and B to D of drawing data 1 and the fields e and f to m of drawing data 2 are located on the sample such that the fields are partly overlapped.
Next, the process of determining the field size is explained.
The field size is determined by the maximum deflection width in such a range that deflection distortion occurred when electron beam is electrically deflected does not affect the pattern. FIGS. 5A to 5D are illustrations showing deflection distortions within a field. FIG. 5A shows an ideal field shape by a dotted line. In contrast, FIG. 5B shows an actual field shape before adjusting the deflection distortion of beam. The actual field shape before adjusting the deflection distortion of beam has a deflection distortion of 0.065 .mu.m(point A) at the maximum, comparing with the ideal field shape in FIG. 5A. Since there will occur a failure in pattern connection when the maximum value is 0.065 .mu.m, the deflection distortion is adjusted before drawing. The process is conducted such that several fields are first laid adjacent to each other as shown in FIG. 5D and then the amount of connection deviation (amount of deflection distortion) at the respective field boundaries is measured. Then, to this distortion, the amount of distortion is approximated by a certain correction formula. From the approximated value, an approximation correction coefficient is generated, and then the correction of distortion is conducted based on this correction coefficient to adjust the boundary connection. However, there occurs a remainder of correction due to a tertiary or higher distortion or a measurement error in measuring the distortion, therefore even after adjusting the deflection distortion, a deflection distortion of 0.031 .mu.m(point B) at the maximum is left as shown in FIG. 5C. However, the connection deviation at field boundary can be corrected to be so smaller than that before the correction. FIGS. 6A to 6D show the case that 0.2 .mu.m patterns are actually connected with each other. When there is a deviation of 0.065 .mu.m as shown in FIG. 6A, a drawing failure, nearly equal to disconnection, occurs in the drawn resist pattern as shown in FIG. 6C.
However, for a deviation of 0.031 .mu.m, such a drawing failure does not occur, as shown in FIG. 6D. The above field connection correction is adjusted at the outermost part of the field (position where beam is most deflected), but like distortion is left also within the field.
Such an example is shown in FIG. 7, where the inside of the field is divided into 25 blocks and the distortion amount at the respective positions inside the field is measured. In this example, there is a connection deviation of 0.031 .mu.m(point B) at the outermost part of the field and there is a connection deviation of 0.028 .mu.m(point C) at the maximum inside the field. Such a deflection distortion left inside the field is caused by the remainder of correction in correcting the deflection distortion and the performance of an amplifier to control the amount of beam deflection. An example of amplifier performance is shown in FIG. 8, where an error of about 0.01.mu.m exists depending on the amount of beam deflection and direction of deflection. Thus, there also occurs deflection distortion inside the field.
In electron-beam-drawing a custom LSI, there are multiple drawing data within a chip, as explained in the above conventional technique. Problems occurring when this chip is drawn by the S & R method are explained below.
When there are drawing data 1, 2 within a chip as shown in FIGS. 4A to 4E, each drawing data is divided into fields. Therefore, as shown in FIG. 9, there must exist fields which overlap partially within the chip. There are some fields which overlap partially, in which field A of drawing data 1 and field e of drawing data 2 are included. Problems occurring when fields A and e are electron-beam-drawn are explained below.
As described earlier referring to FIG. 7, there is a distortion of 0.028 .mu.m inside the field even after adjusting the deflection distortion. In this case, the amount of deviation in pattern drawing within field is 0.028 .mu.m at the maximum. Hereupon, as explained earlier referring to FIGS. 6A to 6D, when 0.20 .mu.m patterns are connected with each other, a drawing failure, such as disconnection, in the resist pattern does not occur even for a connection deviation of 0.031 .mu.m. Namely, between patterns within one field, no drawing failure occurs. However, for the chip to be drawn in this example, fields which overlap partially are existing. FIGS. 10A to 10C are enlarged views showing fields A, e which overlap each other. At point D of field A, as shown in FIG. 10A, there is a deflection distortion of 0.028 .mu.m. On the other hand, at point E of field e, as shown in FIG. 10B, there is a deflection distortion of 0.024 .mu.m. While fields A, e with such distortions overlap partially, patterns within field A and patterns within field e are connected on the sample as shown in FIG. 9. When fields A, e are overlapped partially as shown in FIG. 10C, at both point D of field A and point E of field e, there occur distortions in reverse directions on the sample. Therefore, there occurs a deviation amount that the deviation amount (0.028 .mu.m) at point D and the deviation amount (0.024 .mu.m) are added. In this case, the amount of connection deviation can be 0.052 .mu.m (point F) at the maximum. This causes a drawing failure at the connection part between pattern within field A and pattern within field e.
Its actual drawing pattern is shown in FIG. 11, which provides enlarged views of fields A, B, e and h. Since fields A, B and fields e, h each belong to same drawing data, they each are suitably adjacent each other. However, since fields A, e and fields B, h each overlap partially, the connection deviation at the pattern connection parts may increase, thereby causing a drawing failure.